For a scanning signal line drive circuit and a data signal line drive circuit of a liquid crystal display device, shift registers are broadly used for generating a scanning signal supplied to scanning signal lines and determining timing for sampling a data signal from a video signal. The electric power consumption of an electronic circuit increases in proportion to the frequency, load-carrying capacity, and second power of the voltage. Accordingly, a preset drive voltage of circuits including external circuits such as a circuit for generating a video signal supplied to a display panel tend to be lowered in order to reduce the power consumption.
However, in the cases of pixel circuits, a scanning signal line drive circuit, and a data signal line drive circuit which are formed by adopting polycrystalline silicon thin-film transistors in order to secure a large display area, the difference between threshold voltages sometimes reaches a few volts, between substrates or in one substrate. Taking this into consideration, the drive voltage includes a margin for canceling out the influence of the difference between the threshold voltages, so that there is still a room for the reduction of the drive voltage. In the meantime, circuits adopting single-crystal silicon transistors, such as a circuit for generating the video signal, generally have a drive voltage of 5V, 3.3V or lower.
For this reason, from an external circuit, such as the circuit for generating the video signal, to the display panel, a start pulse and a clock lower than the drive voltage of the shift register is supplied. In such a case, the shift register is provided with a level shifter for boosting the start pulse and clock.
To provide such a level shifter, for instance, Japanese Laid-Open Patent Application No. 2001-135093 (Tokukai 2001-135093; published on May 18, 2001) teaches that a start pulse is boosted by a level shifter and then supplied to a flip-flop of the first stage which is a part of the shift register, while a clock is boosted by the level shifter and then commonly supplied to flip-flops of all stages via buffers. In this case, the load on the occasion of driving the buffers equals to the total of the load of one clock line substantially identical in length with a side of the panel in the shifting direction, the load of the off-capacity of a transistor connected to said one clock line, and the like, so that the load is very heavy. Because of this heavy load, the clock supplied to the flip-flops of the respective stages of the shift register greatly delays. For this reason, the arrangement taught by the patent document cannot be used for high-frequency circuits, and hence generally used for low-frequency circuits such as a scanning line drive circuit. Furthermore, in the aforesaid arrangement, the heavy load increases the power consumption. Thus, in high-frequency circuits such as a data signal line drive circuit, each flip-flop of the shift register is provided with a corresponding level shifter.
FIG. 18 is a block diagram showing circuitry of a shift register 1 which typifies the above-mentioned conventional art. The shift register 1 is disclosed by documents such as Japanese Laid-Open Patent Application No. 2000-339984 (Tokukai 2000-339984; published on Dec. 8, 2000, corresponding to US2003/0174115A1; published on Sep. 18, 2003) and Japanese Laid-Open Patent Application No. 2001-307495 (Tokukai 2001-307495; published on Nov. 2, 2001). The shift register 1 is basically made up of a shift register section 2 and a level shifter section 3. On the input sides of n-stage flip-flops f1, f2, . . . , fn−1, and fn constituting the shift register section 2, level shifters ls1, ls2, . . . , lsn−1, and lsn corresponding to the respective flip-flops are provided. On the output side of the flip-flop fn of the last stage, a level shifter lsn+1 is further provided. Furthermore, on the flip-flop f1 (first stage) side, a level shifter ls0 is provided on a stage before the level shifter Is1.
As a drive voltage of the shift register section 2, the level shifter ls0 generates a start pulse SPO, which is, for instance, boosted to about 15V, from a start pulse SP which is supplied from the circuit for generating the video signal and has an amplitude about 5V and an inversion signal SPB which is an inversion of the start pulse SP. In the level shifter section 3, the start pulse SPO is supplied to an enable terminal ENA of the level shifter ls1 corresponding to the flip-flop f1 of the first stage of the shift register section 2. To clock input terminals CK and CKB of the level shifter ls1, a clock signal CK which is supplied from the circuit for generating the video signal and has an amplitude about 5V and an inversion signal CKB which is an inversion of the clock signal CK are supplied, respectively. From an output terminal OUT of the level shifter ls1, the clock signal CK is outputted as long as the enable signal ENA is active HIGH.
An output signal 11 from the level shifter ls1 appears as an output to the outside of the shift register 1, inverted in an inverter invs1, and then supplied to a low-active set input terminal SB of the flip-flop f1 of the first stage. In this flip-flop f1, an output signal 13 is supplied from the level shifter ls3 which is two stages after the flip-flop f1 to a reset input terminal R of the flip-flop f1 so that the output signal 13 is reset, and an output signal q1 from an output terminal Q is supplied to an enable terminal ENA of the level shifter ls2 of the next stage.
In a similar manner, output signals 12 through ln from the respective level shifters ls2 through lsn appears as outputs to the outside of the shift register 1, inverted by respective inverters invs2 through invsn, and supplied to set input terminals SB of the corresponding flip-flops f2 through fn. The flip-flops f2 through fn−1 are reset by output signals 14 through ln+1 supplied from the level shifters ls4 through lsn+1 which are two stages after the respective flip-flops f2 through fn−1. From the output terminals Q of the flip-flops f2 through fn−1, output signals q2 through qn−1 are supplied to the enable terminals ENA of the level shifters ls3 through lsn which are the next stages of the respective flip-flops f2 through fn−1.
Note that, in the odd-stage level shifters ls1, ls3, . . . , the clock signals CK and CKB are supplied to the clock input terminals CK and CKB, respectively. Meanwhile, in the even-stage level shifters ls2, ls4, . . . , the clock signals CK and CKB are supplied to the clock input terminals CKB and CK, respectively. With this, the level shifters ls2 through lsn+1 carry out serial shifting at intervals of a half of the cycle of the clock signals CK and CKB.
The timing of the output signals l1 through ln from the respective level shifters ls1 through lsn is adjusted in the respective delay circuits d1 through dn in such a manner as to prevent the overlap of sampling pulses. Then the output signals l1 through ln appear as sampling pulses sl1 through sln, after passing through the buffers b1 through bn. With the help of these sampling pulses sl1 through sln, the scanning signal line drive circuit and the data signal drive circuit serially select the signal lines.
FIG. 19 show waveform charts for describing the operation of the aforesaid shift register 1. In accordance with the clock signals CK and CKB which are reverse-phased (180° out-of-phase) with each other, the start pulses SP each having the length half as much as the cycle of the clock signals CK and CKB are, as described above, serial-shifted by the flip-flops f1 through fn at intervals of a half of the cycle of the clock signals CK and CKB. As a result, the output signals l1 through ln are generated from the start pulses SP. Then, also as described above, the flip-flops f1 through fn−1 are reset by the output signals l3 through ln+1 supplied from the level shifters ls3 through lsn+1 which are two stages after the respective flip-flops f1 through fn−1. The flip-flop fn of the last stage is reset by the output signal ln+1 supplied from the level shifter lsn+1 which is one stage after the flip-flop fn. Furthermore, the level shifter lsn+1 of the last stage is reset in a short period by the output signal ln+1 from the level shifter lsn+1 itself, via the flip-flop fn of the previous stage.
In the shift register 1 being thus described, the flip-flops f1 through fn are set-reset flip-flops (SR-FF), and the positive-phase output signals q1 through qn from these flip-flops f1 through fn are used for controlling the operation of the level shifters ls2 through lsn+1 which are one stage after the respective flip-flops fn through fn. Thus, the level shifters ls2 through lsn+1 operate only when the output signals q1 through qn are active. As FIG. 19 shows, therefore, during the first half of the active period of each of the level shifters ls2 through lsn, the first half corresponding to a half of the cycle of the clock signals CK and CKB, the level shifters ls2 through lsn do not contribute to the shifting of the flip-flops f2 through fn (the shifting of the flip-flops f1 through fn−1 of the previous stages is realized if the output signals q1 through qn−1 are switched to be active before the timing at which the clock signals CK and CKB is switched to the next signals), so that the operation of the level shifters ls2 through lsn during the first half of the active period is redundant.
On the other hand, when the level shifters ls1 through lsn+1 are in operation, a stationary current flows in the level shifters ls1 through lsn+1, so that the level shifters ls1 through lsn+1 consume electric power. In case that the level shifters are a voltage-driven type, an input switching element to which the clock signal is supplied is turned on only when the supplied clock signal is active, so as to consume low amounts of power. However, the amplitude of the clock signal has to be higher than the threshold voltage of the input switching element, and this hampers the reduction of the power consumption. For this reason, the level shifters must be a current-driven type with which level-shifting of an input signal by which the input switching element is turned on/off is achieved without no hindrance, even if the amplitude of the input signal is lower than the threshold voltage of the input switching element, so that the input switching element to which the clock signal is supplied is always turned on when the level shifters are in operation, thereby consuming large amounts of power. As a result, the power consumption of a device including the shift register 1, e.g. a liquid crystal display device, is large, so that the battery power quickly burns in the cases of small portable devices and mobile phones, and hence the operating time of such devices is short.
Meanwhile, Japanese Laid-Open Patent Application No. 2001-356728 (Tokukai 2001-356728; published on Dec. 26, 2001, corresponding to US2001/0043496A1; published on Nov. 22, 2001) teaches in FIG. 21 that a clock signal is supplied to a gating circuit, and a signal level-shifted by the gating circuit is supplied to a flip-flop, so that an output pulse is fetched from the flip-flop. According to this document, when the length of the-output pulse from the flip-flop is equivalent to one pulse (a half of the cycle) of a clock signal, the operation time of the gating circuit is equivalent to one pulse of the clock signal. However, when the length of the output pulse is equivalent to not less than two pulses of the clock signal, the operation time of the gating circuit is also equivalent to not less than two pulses of the clock signal. In this manner, as the length of the output pulse increases, the power consumption of the gating circuit increases.